In recent years, new fine processing techniques have been developed as the LSI is highly integrated and exhibits high performance. The chemical mechanical polishing (hereinafter, simply referred to as CMP as well) method is also one of them and is a technique that is frequently used for the flattening of the interlayer insulating film, the formation of metal plug and the formation of embedded wiring (damascene wiring) in the LSI manufacturing process, especially the multilayer wiring forming process.
A general method of CMP is a method in which the polishing pad is pasted onto a circular polishing table (platen), and the polishing pad surface is wet with a polishing agent, the surface on which a metal film is formed of the substrate is pressed against the polishing pad, the polishing table is rotated in a state in which a predetermined pressure (hereinafter, simply referred to as the polishing pressure as well) is applied from the back surface thereof, and the convex portion of the metal film is removed by the mechanical friction between the polishing agent and the convex portion of the metal film.
On the other hand, tantalum, a tantalum alloy, a tantalum compound or the like is formed on the lower layer of copper, a copper alloy or the like which is the wire as a barrier layer for preventing copper diffusion into the interlayer insulating film. Hence, the exposed barrier layer except the wiring part embedding copper or the copper alloy needs to be removed by CMP.
In order to form each wiring layer, it is general that first, CMP of metal film which removes the excess wiring material attached by the plating method or the like (hereinafter, also referred to as the “metal film CMP”) is performed over one stage or a multistage, and then CMP which removes the barrier layer exposed to the surface by the previous CMP (hereinafter, also referred to as the “barrier layer CMP”) is performed. However, there is a problem that the so-called dishing that the wiring portion is excessively polished or a surface defect such as erosion and fang is caused by the metal film CMP.
In order to decrease dishing, it is required to finally form a wiring layer having less steps such as dishing or erosion by adjusting the polishing rate of the metal wiring portion and the polishing rate of the barrier metal portion in the barrier layer CMP performed after the metal film CMP. In other words, it is desirable that the polishing rate of the barrier layer or the insulating film be moderately high in the barrier layer CMP since dishing that the wiring portion is polished faster or erosion as a consequence of the dishing occurs is a case in which the polishing rate of the barrier layer or the interlayer insulating film is relatively slower compared to the metal wiring portion. This is because it is also desirable in that it is required to relatively increase the polishing rate of the barrier layer or the insulating film from the reasons as described above since dishing is actually often caused by the metal film CMP in addition to that there is a merit of increasing the throughput of the barrier layer CMP.
In addition, it is also required to suppress fang as a surface defect. As one factor to cause fang, it is considered that the components contained in the polishing liquid is unevenly localized at the boundary surface between the wiring layer and the region other than the wiring layer such as the carrier layer or the interlayer insulating film and thus the vicinity of the boundary surface is excessively polished. For example, it is considered that the polishing rate locally increases at the boundary surface when the abrasive grain component contained in the polishing liquid is present at a high concentration in the vicinity of the boundary surface and thus the boundary surface is excessively polished.
As described above, as a technique to decrease the surface defect such as erosion or fang while maintaining a relatively higher polishing rate for the barrier layer and the interlayer insulating film with respect to the wiring layer, a polishing liquid which is a polishing liquid for polishing the copper film, barrier metal film and interlayer insulating film of a semiconductor integrated circuit and contains silica particles having a specific silanol group density and an organic acid is disclosed, for example, in JP 2010-041029 A and JP 2010-041027 A.